The present invention relates to a method of manufacturing a semiconductor device comprising a high-voltage transistor. The present invention has particular applicability in manufacturing nonvolatile semiconductor memory devices requiring a high programming voltage.
Conventional nonvolatile semiconductor memories such as flash electrically erasable programmable read only memories (Flash EEPROMs), typically comprise a floating gate memory cell, which includes a source region, a drain region and a channel region formed in a semiconductor substrate, and a floating gate formed above the substrate between the channel region and a control gate. One method of programming or erasing a floating gate memory cell, utilizing a phenomenon known as Fowler-Nordheim tunneling, comprises applying a voltage differential, such as about 16 volts to about 23 volts, to the control gate while the channel region is kept at a low voltage, such as about 0 volts to about 2 volts, to force electrons into the floating gate. This movement of electrons is referred to as programming, and the high voltage (i.e., about 16 to about 23 volts) applied to the control gate is known as program voltage. A similar method is employed to erase the memory cell by reversing the direction of bias to force the electrons out of the floating gate.
Flash memory systems conventionally comprise a two-dimensional array of floating gate memory cells. One such array architecture is called NAND architecture, which typically includes several strings, known as NAND strings, of floating gate memory transistors, each transistor coupled to the next transistor in the string by coupling the source of one device to the drain of the next device to form bit lines. A plurality of word lines, perpendicular to the NAND strings, each connect to the control gate of one memory cell of each NAND string.
To supply program voltage on demand to each of the word lines, a CMOS transistor referred to as a xe2x80x9crow selectorxe2x80x9d is employed at one end of each word line. In order to attain an acceptable level of performance and reliability, this transistor must exhibit low leakage from drain to source and a low body effect so that its threshold voltage is not excessively high. Conventional processing techniques require many separate photolithographic masking steps to manufacture this transistor. The large number of masking steps raises the production cost of the flash memory device and increases the probability of defects in the finished device.
There exists a need for simplified methodology in manufacturing a high voltage, high performance transistor with fewer processing steps, thereby reducing manufacturing costs and increasing production throughput.
An advantage of the present invention is a simplified method of manufacturing a high voltage transistor which exhibits low leakage and low body effect.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by method of manufacturing a semiconductor device, which method comprises isolating a substantially rectilinear active area on a main surface of a semiconductor substrate, the active area comprising a first source/drain region and a second source/drain region, each having a source/drain width and a source/drain length, separated by a channel region having opposing ends not abutting either of the source/drain regions along the source/drain length; providing a field implant blocking mask over the channel region, the field implant blocking mask having a pair of substantially rectangular notches, each notch protruding over the channel region a predetermined distance along the source/drain width from one of the opposing ends of the channel region; and implanting impurities to form a field implant in the substrate.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.